参考文献
天野 英晴, FPGAの原理と構成, オーム社
坂井 修一, 論理回路入門, 培風館
演算子の優先順位 - The Veryl Hardware Description Language,https://doc.veryl-lang.org/book/ja/05_language_reference/04_expression/01_operator_precedence.html
演算子 - The Veryl Hardware Description Language,https://doc.veryl-lang.org/book/ja/05_language_reference/02_lexical_structure/01_operator.html
The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.3. Immediate Encoding Variants
The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 37. RV32/64G Instruction Set Listings
The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.4. Integer Computational Instructions
The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.5. Control Transfer Instructions
The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 Figure 10. Encoding of mtvec MODE field.
The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 3.1.7. Machine Trap-Vector Base-Address Register
The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 15. RISC-V Privileged Instruction Set Listings
David Patterson, John Hennessy(著),成田 光彰 訳, コンピュータの構成と設計 MIPS Edition 第6版 [上] ~ハードウエアとソフトウエアのインタフェース~, 日経BP