参考文献

[1]

天野 英晴, FPGAの原理と構成, オーム社

[2]

坂井 修一, 論理回路入門, 培風館

[3]

演算子の優先順位 - The Veryl Hardware Description Language,https://doc.veryl-lang.org/book/ja/05_language_reference/04_expression/01_operator_precedence.html

[4]

演算子 - The Veryl Hardware Description Language,https://doc.veryl-lang.org/book/ja/05_language_reference/02_lexical_structure/01_operator.html

[5]

The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.3. Immediate Encoding Variants

[6]

The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 37. RV32/64G Instruction Set Listings

[7]

The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.4. Integer Computational Instructions

[8]

The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture version 20240411 2.5. Control Transfer Instructions

[9]

The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 Figure 10. Encoding of mtvec MODE field.

[10]

The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 3.1.7. Machine Trap-Vector Base-Address Register

[11]

The RISC-V Instruction Set Manual Volume II: Privileged Architecture version 20240411 15. RISC-V Privileged Instruction Set Listings

[12]

David Patterson, John Hennessy(著),成田 光彰 訳, コンピュータの構成と設計 MIPS Edition 第6版 [上] ～ハードウエアとソフトウエアのインタフェース～, 日経BP

[13]

PYNQ-Z1 Reference Manual - Digilent Reference, https://digilent.com/reference/programmable-logic/pynq-z1/reference-manual